1. Field of the Invention
This disclosure relates to testing of integrated circuits, in particular to measurements of voltage transitions on internal nodes of integrated circuits.
2. Description of the Related Art
Measurements of voltage transitions on internal circuit nodes are needed during the development and testing of complex integrated circuits (xe2x80x9cICsxe2x80x9d hereafter). In some instances mechanical probing and beam (electron beam) probing can provide the requisite information. However, when flip-chip packaging technology is used, mechanical and beam probe access to the front (metal connection) side of the IC die is blocked.
It is known to use a light beam to measure voltage at an internal circuit node in a conventional flip-chip packaged IC. (An example of a circuit mode is an output or input terminal of a logic gate but it may be any point on an electrical connection in the circuitry on the IC.) An example of a conventional system for measuring circuit voltage at an internal circuit node of an IC using light is the IDS2000 system manufactured by Schlumberger Limited, and described in U.S. Pat. No. 5,905,577. Such a light beam is focused on a circuit element such as a diode (P-N junction) in the IC where the measurements are desired. The diode is electrically connected to the circuit node. At the same time, the IC is conventionally exercised by applying to its input terminals electrical signals in the form of commands defining test patterns. In response to the applied test patterns (vectors), voltage transitions take place at the circuit node, which is merely a point on an electrical connection to the circuit element. The light reflected from the circuit element is modulated by changes in the electrical state of the circuit node, in response to the test patterns. Thus the reflected light provides a measure of voltage transitions (signals) at the circuit node.
There are drawbacks associated with this method. First, the modulation of the reflected light beam is very weak and averaging techniques must be used to obtain low noise measurement waveforms. Second, as semiconductor device (transistor) feature sizes shrink on ICs, it is expected that this modulation will become weaker. Third, many circuit problems are intermittent, (e.g., in logic circuits) so that test averaging will produce false results unless the IC activity is exactly repeated for every test pattern cycle.
Electrical access to such internal circuit nodes can be achieved by providing an on-chip circuit called a scan chain. This test method modifies the otherwise conventional flip-flops used in the IC, providing a two input data selector to the D input terminal of each flip-flop. The data selector control signal for all the flip-flops is a common signal called Scan Enable. With Scan Enable in the low logic state, the data selector is set for normal IC operations. However, the Q output terminal of each flip-flop is coupled to the normally unused data selector input of another flip-flop. When Scan Enable is in the high logic state this path is enabled, forming a continuous shift register structure from all the modified and connected flip-flops. Thus serial data representing an arbitrary logic state can be loaded from one of the IC input pins into the shift register with Scan Enable high, and normal IC operation begun from this arbitrary internal state by switching Scan Enable low. Also at any point in the normal operation of the IC, Scan Enable can be made logic high, thus latching the logic state of all internal nodes into the shift register. The contents of the shift register can then be clocked to an output pin for analysis. For a detailed description of scan test methods see Alfred L. Crouch, xe2x80x9cDesign For Test For Digital IC""s And Embedded Core Systems,xe2x80x9d Prentice Hall, 1999.
However, the scan chain operations cannot be performed at full device operating speed. Thus at low speed all faults may be located, but faults occurring only at high speed may elude isolation in time and position. Latching of the scan chain can be done with the DUT (device under test, referring to the IC under test) operating at full clock speed, thereby obtaining a xe2x80x9csnap shotxe2x80x9d of the IC internal nodes at an instant in time. However, it is difficult to distribute simultaneously to the scan chain the latching clock pulse, or at least distribute the latching clock pulse within a small fraction of the device clock period. Because of this, the data obtained in this manner is suspect. The on-chip time relationship between voltage transitions on two nodes is not accurately represented in the data obtained in this manner. This latching pulse skew distribution problem becomes worse as the number of active circuits contained in a DUT (Device Under Test) increases.
Thus it is desirable to provide high timing accuracy diagnostic latching ability inside a DUT to obtain reliable measurements of faults occurring at high speed and also intermittent faults. It is desirable to provide high timing accuracy latching at any location in a DUT, and to provide high timing accuracy latching simultaneously at two or more nodes. It is further desirable to provide high timing accuracy latching with a predetermined and controlled delay.
This disclosure is directed to a method and apparatus that overcome aforesaid shortcomings of the prior art. The method and apparatus are non-invasive and non-destructive of the IC under test and do not affect normal operation of the IC.
This disclosure is mostly directed to testing of, e.g., flip-chip packaged integrated circuits (ICs) and also conventionally packaged ICs with access to the backside of the IC die (the die is the semiconductor substrate without its leads, heat sink, or package). Each IC to be tested using the method and apparatus of this disclosure is fabricated with on-chip light sensitive devices, such as diodes. The light sensitive devices are each electrically coupled to one or more on-chip (on-die) D type flip-flops (flip-flops hereafter) or similar storage elements. Each circuit node whose electrical state is of interest is also coupled to one of the flip-flops. The IC device under test (DUT) is prepared for testing by opening the package, thereby exposing the backside of the die without disturbing its electrical functioning. The back side is the side opposite the principal surface on which the transistors are formed. In case of a flip-chip package, the backside is the side opposite the surface on which the bond between the die and the substrate is formed. The exposed die surface can be thinned, polished, and anti-reflection coated to improve optical transmission. In one embodiment, the light sensitive devices (e.g., photodiodes) are spaced apart from the remainder of the IC circuitry and from each other so that, e.g., laser illumination incident thereon can be focused thereon without need for extreme accuracy in terms of location.
A die packaged to allow optical access to the front surface only could also tested by the described method, if the optical path to the light sensitive element was clear of opaque obstructions such as metal lines and power planes. A detailed description of relevant chip mounting technologies is given in xe2x80x9cLow Cost Flip Chip Technologiesxe2x80x9d by John H. Lau, McGraw Hill 2000.
The DUT, prepared as described above, is conventionally exercised (tested) by a suitable computer generated test program run on an IC test apparatus applying a test pattern to the signal input pins (terminals) of the DUT. While the test pattern is being run, a light pulse is directed by conventional beam steering and focusing optics in the test apparatus through the exposed backside surface of the DUT die onto one or several of the on-chip light sensitive devices. In response, each such light sensitive device generates an electrical pulse. This electrical pulse is used as clock pulse to latch the logic state of the associated circuit node at the instant of the clock pulse into an associated on-chip flip-flop. The logic state of the circuit node at the instant of the clock pulse is thus stored in the flip-flop, and can be read out later. The readout can be accomplished by having a direct connection between each flip-flop output terminal and one of the DUT pins. Another readout method is to use a conventional scan chain. In this case the flip-flop output terminals are treated as extra nodes whose state can be read out serially by using additions to the DUT scan chain. The pin count of the DUT is not increased.
After the data in each such flip-flop is readout and stored in the conventional data analysis equipment associated with the test apparatus, the cycle is repeated. The cycle of running the test pattern, sampling, and storing can be repeated many times with the sampling time having different values each repetition. The stored results represent the change in logic state of the tested node during these times. The light pulse can be directed at light sensitive devices at separate locations on the DUT without any appreciable change in its time of arrival at these various locations. Therefore it is possible to obtain logic data from widely separate circuit nodes with confidence that the recorded time relationships are a very accurate representation of the actual on-chip electrical activity.